Comments

Jerehmia 18th Apr 2023

Oh man sorry for posting the link, I didn't notice this got to fp. Congrats :)
Jerehmia 18th Apr 2023

Just for reference, here's how I would implement the adder id:2999209
tptQuantification 18th Apr 2023

0x2 0 0 0 000
tptQuantification 18th Apr 2023

Or in hex: 0(oops not obligitory, i dont know) 0 (ALU opcode) 0 (processor/data handling opcode) 0 (I DONT KNOW) 000 (read/write memory adress)
tptQuantification 18th Apr 2023

Operation register: 1(obligitory bit) 0000 (ALU opcode) 0000 (processor/data handling opcode) 0000 (I DONT KNOW) 0000 0000 0000 (read/write memory adress)
tptQuantification 18th Apr 2023

so allocation planning: 0x1FFFFFFF operation register + 2 0x1FFFFFFF data registers
tptQuantification 18th Apr 2023

@R33sesK1ng yes yes yes i've been doing that a bunch. whenever the update order doesnt jive, i make it do its thing with inst sprk timing.
Jerehmia 18th Apr 2023

@R33sesK1ng delaying the SPRK would probably cause other trouble here, he's checking the carry FILTs for a certain value to stop the calculation so it's good practice to make sure that only legal values appear on those FILTs and no intermittrent illegal values because those could stop the calculation or screw up the result in other ways.
R33sesK1ng 18th Apr 2023

@tptQuantification, If you're having some trouble about #ID order, you could stagger the updates with SPRK propagation across conductors. It could make the circuitry less clean without planning, but it saves the headache in the longrun.
R33sesK1ng 18th Apr 2023

+1 +Fav

The Powder Toy

wip alu by tptQuantification

Comments