Aeralius
Aeralius
7 / 1
3rd Feb 2019
3rd Feb 2019
Just sharing it here. While working on a CPU. Trying to stay with "Classic" electronincs and yet making it compact as possible for obvious reasons.

Comments

  • INFINITY-BOI
    INFINITY-BOI
    17th Apr 2020
    how did u made so small full adder :v ?
  • NoVIcE
    NoVIcE
    17th Feb 2019
    Sorry for the delay. I actually mean having, like, 2 half adders (1 full adder). That's the whole adder. Then you reuse that one full adder n times, for 2 n-bit numbers.
  • Aeralius
    Aeralius
    3rd Feb 2019
    Actually i found bugs in all of them. I am working on having them work on a single pulse. Right now they barely work on holding spark
  • Aeralius
    Aeralius
    3rd Feb 2019
    ID:2381869 for the half adder design
  • Aeralius
    Aeralius
    3rd Feb 2019
    @NoVIcE, i am not sure what you mean, but it sounds like what i am already doing. Do you have any examples? The current method uses 2 half adders to make a full adder, then stacking it 8 times for 8 bit. Inverting input B using a XOR to subtract.
  • NoVIcE
    NoVIcE
    3rd Feb 2019
    Interesting. BTW you can make an 1-bit adder, repeating itself n-bit times to add/subtract 2 n-bit numbers. Become slower but way smaller.