unnick
20th Feb 2019
22nd Feb 2019
with the recent addition of ldtc to tpt, i decided to waste my ti- i mean try to make a ram module which can be written/read to/from any number of times, which will be useful in trying to make subframe computers faster. do whatever you want with it.
subframe
electronics
multiport
Comments
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still dont understand the dray.
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thank you unnick, very cool
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@unnick I'll PM you.
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Schmolendevice: okay, i saw your stackable adder before when looking at all your saves, and what instruction set did you create?
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@unnick As for "executing multiple instructions per frame", I was looking into that three years ago in grade 12 when I tried to do a science project on superscalar CPU architecture. I had developed the basis of a compact instruction set to support such, but my thirst for smaller electronics and pretty documentation conventions delayed that. Then engineering school happened.
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@unnick Why yes. University happened. Almost a year ago was my last update of TPT's smallest adder that can be "stacked horizontally" at a density of 8 pixels per adder; I had a finished Kogge-Stone adder of similar form factor which I want to make even smaller and waste less bits on "bit retention".
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Schmolendevice: wait you are alive?
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Killedbydeath2: you can also make metal loops that can either contain a rotating spark or not have one, and bray could be used too.
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Timothysparrow: basically yeah.
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Cool4Cool: instruction pipelining wont be that useful in tpt, because you can just put the individual stages of the pipeline downwards and they will get executed one after the other. what WILL make computers faster is making them execute multiple instructions per frame, which would actually be pretty easy, the complicated parts are just the registers and the multi-port ram needed.