sprk* (comment too short)
		
		
			
			if you're talking about AND mode in full adder, I saw some adders using lsns and tried to make my own version. In this case, DTEC looks for a bray, gets life 1, and lsns changes the filt's stage, allowing a type of AND gate.
		
		
			
			I don't know if it's different. I just used a full adder and some logical processes using the filt.
		
		
			
			Awesome, how is this different from using AND mode FILT?