Data width: 8 bits Instructions: 16
Clock rate: 2 Hz Address width: 10 bits
[ A ] Accumulator
[ B ] B register
[ C ] C register
[ P. C. ] Program Counter
[Z] [C] Processor Status Flags
2 bytes per instruction.
First Byte(Instruction, Register, Memory page)
bit 7 6 5 4 3 2 1 0
------- --- --- (Respectively)
Register selector:
bit 3 2
--------------------
0 0 Register B
0 1 Register C
1 0 Direct Data
1 1 Memory Access
Second Byte(Direct Data/Memory Address)
*Note that it uses the less significant 2 bits from first byte to set the memory page location.
%10101100, %01001011
-- --------
Memory Page Memory Address (10 bits total for Full Memory Access)
If Fetch is ON....
Clock cycle 1: [Memory address IN] [Counter OUT]
2: [Instruction decoder IN] [Memory page IN] [Register selector IN] [Memory OUT] [Counter INCREMENT]
3: [Memory address IN] [Counter OUT]
4: [Addres/Direct data Register IN] [Memory address IN] [Memory OUT]
5: [Counter INCREMENT] [Fetch OFF] [Instruction EXECUTE]
0000- NOP: No OPeration. It is simply a void instruction cycle. It may be useful to let the processor wait for other
devices operations like an I/O port.
0001- LDA: LoaD to Accumulator. Loads data stored wherever the Register Selector has... selected.
For instance: If bits 3 and 2 are 0 and 1 respesctively, Will load data from Register C.
0010- STA: STore Accumulator. Store data from accumulator to wherever the Register Selector indicates. (*Data cannot be stored in Direct Data/Address Register)
0011- ADD: ADDs to accumulator a value stored wherever the Reg. Sel. indicates.
0100- SUB: SUBtracts from accumulator a value stored wherever the Reg. Sel. indicates.
0101- NOT: Inverts the accumulator.
0110- XOR: eXclusive OR. Logical exclusive OR the accumulator bits with data stored where Reg. Sel. indicates.
0111- ROL: ROtate Left. Shift bits in accumulator to the left. (The same as: Accumulator x2)
1000- CLC: CLear Carry flag.
1001- CLZ: CLear Zero flag.
1010- JMP: JuMP to memory address specified in bits 1 and 0, and the second byte. (Bits 3 & 2 must be always set)
1011- JIZ: Jump If Zero. Like JMP, but only if Zero flag is set. (**)
1100- JNZ: Jump if Not Zero. Like JMP, but only if Zero flag is not set. (**)
1101- JIC: Jump If Carry. Like JMP, but only if Carry flag is set. (**)
1110- JNC: Jump if Not Carry. Like JMP, but only if Carry flag is not set. (**)
1111- HLT: HaLT. Stop the clock(Does not Reset the chip).
Instruction examples:
LDA #$0E ==> %0001 10 00, %00001110 (Load Accumulator with number 14 = $0E)
STA $265 ==> %0010 11 10, %01100101 (Store Accumulator in Memory Address 613 = $265)
SUB C ==> %0100 01 00, %00000000 (Subtract data in Register C to Accumulator)
JMP $23 ==> %1010 11 00, %00100011 (Jump in Program to Memory Address 35 = $23)
(Prefixes: #=Direct Data (From program). $=Hexadecimal Number. %=Binary Number.)
Notes:
(* To understand this manual, you will need to already know binary system and basic logic gates)
(** Before check the zero/carry flag, you will need to perform a STA instruction for flag update)
(*** You may need a proper memory to fit the 650E Fetching need)
Eliasdbr Semiconductors ©1986
//I hope you like my job! I will frequently see the saves comment if you want to report bugs or
//post you project made with this processor =D
Great job! That is a very small computer. Oh and that sweet dank 650E logo...
Good work! You've made a very cool machine.
Thank you very much guys!
@12Me21 You're right, but this ALU only has the Left Shift operation :( and I think there is no way to do right shift with other operations. If you could help me... I would be glad!
I'll do a revision to this Processor when I have enough sugestions!