Tesla A10D28

Vocabulary:
     Qyte - A unit of five bits. (Used for discussing memory addressing) A portmanteau of "Quint" and "Byte".

Description:
     The Tesla A10D28 is a small microprocessor unit at 38x32px in size.

     The T-A10D28 has 8 internal registers:
          IP - 5-Bit  - Instruction Pointer. Low qyte of the address of the next instruction.
          PR - 5-Bit  - Page Register. The high qyte used in all memory references.
          RP - 2-Bit  - Register Pointer. Not a true register, is simply representative of the reader head's position in the register file.
          r0,
          r1,
          r2,
          r3 - 28-Bit - General Purpose Registers. The specific register that it accessed when interacting with the GP registers ("LD bus,r", for example) is determined by the 2-Bit Register Pointer.
          l  - 28-Bit - Logic Register. Used for logical, bit-comparison operations.

     The A10D28 has 4 external ports:
          DIN  - Data In, top face.
          AOUT - Address Out, left face.
          DOUT - Data Out, right face.
          OUT  - Standard output, bottom face.

     Busses:
          There are two hardware busses on the A10D28, the Data Bus and the Instruction Bus.
          Every time the CPU recieves a byte as an instruction (as opposed to as data), the byte is put onto Instruction Bus. Once an instuction has been copied to the Instruction Bus, the instruction is able to be enacted.
          The data bus can be written to by the internal registers, or by bytes recieved as data. Since that Data Bus is seperate from the Instruction Bus, the value on the Data Bus is persistent until intentionally rewritten. Due to this, the Data Bus, or just "bus", is treated as more of a register when programming for the CPU.

Coding:
     The A10D28 does not have your typical instructions. Instead, the A10D28 has 17 "instructionlets".
     Instructionlets can be combined to create higher functions. Ex: "Res RP; Mov RP 1; Mov RP 2; LD bus,r;" is equivalent to "LD bus,r3" 
     Since the A10D28 does not have a program counter, each instruction must contain the address of the next instruction. This is the "Next Instruction Addres" as the low qyte combined with the PR register as the high qyte. Every time an instruction is taken into the processor, the 5-Bit "Next Instruction Address" is loaded into the IP register automatically. 
     Each instructionlet has a respective bit (listed below) that means, when the bit is set, the instructionlet will be carried out upon execution of the instruction.

111111111111
BA9876543210FEDCBA9876543210 - Bit#
[---][---]||||||||||||||||||LD bus,(ap) - Loads a byte from memory onto the Data Bus. The low qyte is the "ap" section of the instruction and the high qyte is PR.
|    |    |||||||||||||||||Res rp ------- Resets the position of the register pointer.
|    |    ||||||||||||||||Mov rp,1 ------ Moves the register pointer up by one position.
|    |    |||||||||||||||Mov rp,2 ------- Moves the register pointer up by two positions.
|    |    ||||||||||||||LD bus,r -------- Loads the GP register being pointed to by RP into the data bus.
|    |    |||||||||||||LD r,bus --------- Loads the data bus into the GP register being pointed to by RP.
|    |    ||||||||||||LD l,bus ---------- Loads the value of the data bus into the Logic Register.
|    |    |||||||||||And bus,l ---------- Performs a bitwise AND of l and the bus. The result is put onto the bus.
|    |    ||||||||||Or bus,l ------------ Performs a bitwise OR of l and the bus. The result is put onto the bus.
|    |    |||||||||Xor bus,l ------------ Performs a bitwise XOR of l and the bus. The result is put onto the bus.
|    |    ||||||||Andrl bus,l ----------- Performs a bitwise AND of l and the bus. The result is then rotated left and put onto the bus. If the result is nonzero, the Condition flag is flipped.
|    |    |||||||Set c ------------------ Sets the Condition flag.
|    |    ||||||Inv c ------------------- Inverts the condition flag.
|    |    |||||BRC ap ------------------- Branch on Carry, If the Condition flag is set, IP is set to the [ap] section of the instruction. If not, the IP is set as it normally would be, to the value of the "next instruction" section.
|    |    ||||[LD p,bus] ---------------- Note, all instructions involving 'p' will be implimented in a planned Indexing Expansion Module, and are not connected in the standard CPU model. 
|    |    |||Out bus/[LD (p),bus] ------- Out bus outputs the contents of the bus through the CPU's OUT port.          
|    |    ||[LD bus,(p)]
|    |    |LD PR,ap --------------------- Sets the Page Register, the high qyte of instruction refrences, to the [ap] section of the instruction.
|    |Next Instruction Address
|Alternative Pointer (ap)

Example Fibonacci Sequence program:
Addrs:SB  AP    IP    Instruction Data  # Mnemonic
00000:10 00000 00001 000000000000011010 # LD bus,r2; ins i+; @fibLoop;
00001:10 00000 00010 000000000000100110 # LD r1,bus; ins i+;
00010:10 00000 00011 000000000000010010 # LD bus,r0; ins i+;
00011:10 00000 00100 001000000000101010 # LD r2,bus; Out bus; ins i+;   
00100:10 00000 00101 000000000000010010 # LD bus,r0; ins i+; @addLoop;
00101:10 00000 00110 000000000001010110 # LD l,bus; LD bus,r1; ins i+;
00110:10 00000 00111 000001101000000000 # XOR bus,l; Res c; ins i+;
00111:10 00000 01000 000000000000100010 # LD r0,bus; ins i+; 
01000:10 00000 01001 000000000000010110 # LD bus,r1; ins i+;
01001:10 00000 01010 000000010000000000 # Andrl bus,l; ins i+;
01010:10 00100 00000 000010000000100110 # LD r1,bus; JP c,addLoop; ins fibLoop

@Chemlab (View Post)

 Yeah, this archetecture is very unusual to say the least. I had to do away with a lot of things to make it so small. Ex. Had to remove the ALU, so no addition instruction. And had to remove the Control Unit, so, no proper instructions, just "instructionlets".

Feel free to message me with questions if need be.

So, after this doc has been described by a journalist as "bewildering", perhaps I should elaborate on it a bit? Maybe add some examples?
To be fair, this is probably one of the most esoteric architectures I've made.




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